High impedance passive switched capacitor common mode feedback network

A method comprising:

• comparing a sensed common mode voltage to a desired common mode voltage in a first phase of operation;
• coupling a first capacitor to a second capacitor in an anti-parallel layout in a second phase of operation to maintain a differential charge across the first capacitor and the second capacitor;
• and
• updating the sensed common mode voltage based at least in part on the comparing during the second phase of operation.

A switched capacitor circuit comprising:

• means for comparing a sensed common mode voltage to a desired common mode voltage in a first phase of operation;
• means for coupling a first capacitor to a second capacitor in an anti-parallel layout in a second phase of operation to maintain a differential charge across the first capacitor and the second capacitor;
• and
• means for updating the sensed common mode voltage based at least in part on comparing during the second phase of operation.

A phase locked loop (PLL) circuit, comprising:

• a first circuit having differential output terminals;
• and
• a switched capacitor circuit comprising:
• a first capacitor coupled in series with a second capacitor in a first mode of operation across the differential output terminals of the first circuit, and coupled in an anti-parallel layout in a second mode of operation;
• and
• a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor and on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.