US 2018/0123601 A1 · DELAY LOCKED LOOP TO CANCEL OFFSET AND MEMORY DEVICE INCLUDING THE SAME

Abstract

A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

Claims20

Dependent claims

A memory device comprising:

a clock delay circuit configured to transmit a reference clock to a data output circuit;
and
a delay locked loop including a variable delay circuit and a clock delay replica circuit, the variable delay circuit configured to generate a first clock by delaying the reference clock, and the clock delay replica circuit configured to receive the first clock and replicate the clock delay circuit, the delay locked loop being configured to receive a second clock which is the delayed reference clock from the clock delay circuit, and adjust a delay of the clock delay replica circuit based on the second clock and a third clock output from the clock delay replica circuit.

Dependencies are inferred from the claim text.

Delay locked loop to cancel offset and memory device including the same

Life of this patent

Delay locked loop to cancel offset and memory device including the same

Life of this patent

Abstract

Claims20