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US 2018/0123600 A1Published application
Clock generation circuit, and semiconductor device and system using the same
AssigneeSK hynix Inc.
InventorMyeong Jae PARK
Life of this patent
Estimating the term…
Abstract
A clock generation circuit may include a first clock generator and a second clock generator. The first clock generator may generate a first output clock toggling in synchronization with a rising edge of a first input clock. The second clock generator may generate a second output clock based on a second input clock and the first output clock. The second output clock may have a level changing based on the first output clock, and may be generated at a rising edge of the second input clock.
Claims20
A clock generation circuit comprising:
- a first clock generator configured to generate a first output clock which toggles in synchronization with a rising edge of a first input clock;
- and
- a second clock generator configured to generate a second output clock, which has a level changing based on the first output clock, at a rising edge of a second input clock.
A clock generation circuit comprising:
- a first divided clock generator configured to generate a first divided clock based on a first input clock;
- a second divided clock generator configured to generate a second divided clock based on a second input clock and the first divided clock;
- and
- a first synchronizer configured to generate a second output clock by synchronizing the second divided clock with the second input clock.
1 more element
A semiconductor device comprising:
- a clock buffer configured to receive a clock and generate a first input clock and a second input clock;
- a clock generation circuit configured to generate a first output clock and a second output clock based on the first and second input clocks;
- and
- a delay-locked loop circuit configured to generate a plurality of multiphase clocks based on the first and second output clocks, the clock generation circuit comprising:
- a first divided clock generator configured to generate a first divided clock based on the first input clock;
- and
- a second divided clock generator configured to generate a second divided clock based on the second input clock and the first divided clock.
4 more elements
Dependencies are inferred from the claim text.