Output buffer circuit and memory device including the same

A memory device comprising:

• a memory cell array including a plurality of memory cells;
• a code generation circuit configured to generate a resistance calibration code for determining an output resistance value;
• and
• an output buffer circuit comprising a main driver configured to output a data output signal based on an input data read from the memory cell array,
• wherein the main driver is configured to receive the resistance calibration code, to provide a first output resistance value determined by the resistance calibration code upon the input data, and to provide a second output resistance value determined by an emphasis code different from the resistance calibration code for performing an emphasis operation in an emphasis execution period upon the input data.

A memory device comprising:

• a memory cell array including a plurality of memory cells;
• a termination resistance calibration circuit configured to generate a resistance calibration code for determining an output resistance value;
• and
• an output buffer circuit including a pre-driver and a main driver, and configured to receive an input data read from the memory cell array and output an output data,
• wherein the pre-driver is configured to:
• generate a first driving signal code in response to the input data regardless of the resistance calibration code, and
• generate a second driving signal code in response to the input data and the resistance calibration code,
• wherein the main driver is configured to output the output data to have a first output resistance value in response to the first driving signal code, and have a second output resistance value different from the first output resistance value in response to the second driving signal code.