Low-area, low-power, power-on reset circuit

A power-on reset circuit comprising:

• a first native NMOS transistor configured to generate a reference current
• a current mirror configured to mirror the reference current,
• a comparator transistor configured to receive and compare the reference current with a sense current indicative of a supply voltage;
• and
• second and third native NMOS transistors;
• wherein a sense transistor of the current mirror is coupled to ground via the first native NMOS transistor and the second native NMOS transistor;
• wherein a mirror transistor of the current mirror is coupled to ground via the comparator transistor and the third native NMOS transistor;
• wherein a control node of the comparator transistor is coupled to a control node of the sense transistor and to a control node of the mirror transistor;
• and
• wherein a node coupling the mirror transistor to the comparator transistor provides an output of the power-on reset circuit.

A method for providing a power-on reset signal, the method comprising:

• generating a reference current indicative of a voltage threshold using a first native NMOS transistor;
• providing a sense current from a supply voltage without using a passive device;
• comparing the reference current to the sense current, the sense current indicative of a level of the supply voltage of a circuit responsive to the power-on reset signal;
• setting an output of a comparison circuit to a first state if the reference current is greater than the sense current;
• setting the output of the comparison circuit to a second state if the sense current is greater than the reference current.