Semiconductor device and method of generating power-on reset signal
AssigneeLapis Semiconductor Co., Ltd.
InventorTetsuji Maruyama
Life of this patent
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Abstract
A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.
Claims5
A semiconductor device comprising:
- a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line;
- and
- a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.
A method of generating a power-on reset signal performed in a semiconductor device in which a regulator configured to output a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage to an internal power supply line is formed, the method of generating the power-on reset signal comprising:
- generating a signal which has a first level at which reset is prompted after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted when a voltage value of the internal power supply line has risen as the power-on reset signal.
Dependencies are inferred from the claim text.