Pulse width filtering circuit

A pulse width filtering circuit, comprising:

• an input transition detection circuit arranged to detect a change of state of an input signal, wherein the change of state includes a first transition from a low signal to a high signal, and a second transition from the high signal to the low signal;
• a first delay circuit arranged to determine whether the high signal resulting from the first transition is maintained for longer than a first predetermined period, and, if so, outputting a first output indicative of the first transition, after the first predetermined period elapses following the first transition;
• a second delay circuit arranged to determine whether the low signal resulting from the second transition is maintained for longer than a second predetermined period, and, if so, outputting a second output indicative of the second transition, after the second predetermined period elapses following the second transition;
• and
• a switching circuit operably connected to the first delay circuit and the second delay circuit, and selectively outputting the first output of the first delay circuit and the second output of the second delay circuit, based on the state of the input signal.