Apparatus and method for instant-on quadra-phase signal generator
AssigneeMicron Technology, Inc.
InventorYantao Ma
Life of this patent
Estimating the term…
Abstract
Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is provided communicatively coupled to the first delay circuit and configured to receive the first delayed clock signal at a first input and a second input clock signal at a second input. The first phase mixer may then generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.
Claims20
An apparatus comprising:
- a first input node configured to receive a first input clock signal;
- a second input node configured to receive a second input clock signal, the second input clock signal being substantially complementary to the first input clock signal;
- a third input node configured to receive a third input clock signal, the third input clock signal having a first delay amount with respect to the first input clock signal;
- a fourth input node configured to receive a fourth input clock signal, the fourth input clock signal having a second delay amount with respect to the second input clock signal;
- a fifth input node configured to receive a fifth input clock signal, the fifth input clock signal having a third delay amount with respect to the first input clock signal;
- a sixth input node configured to receive a sixth input clock signal, the sixth input clock signal having a fourth delay amount with respect to the second input clock signal;
- and
- an output block configured to:
- provide a first output clock signal at a first output node responsive, at least in part, to the first and fourth input clock signals,
- provide a second output clock signal at a second output node responsive, at least in part, to the second and third input clock signals,
- provide a third output clock signal at a third output node responsive, at least in part, to the fifth output clock signal, and
- provide a fourth output clock signal at a fourth output node responsive, at least in part, to the sixth input clock signal;
- wherein the first, second, third and fourth output clock signals are different in phase from one another.
The apparatus of claim 3, wherein the first delay amount is substantially equal to the second delay amount and the third delay amount is substantially equal to the fourth delay amount.
An apparatus comprising:
- a first delay circuit configured to receive a first input clock signal and to provide first and second delayed clock signals based, at least in part, on the first input clock signal;
- a second delay circuit configured to receive a second input clock signal and to provide third and fourth delayed clock signals based, at least in part, on the second input clock signal;
- a first buffer configured to provide a first output clock signal based, at least in part, on the first delayed clock signal;
- a first phase mixer configured to provide a second output clock signal based, at least in part, on the second input clock signal and the second delayed clock signal;
- a second phase mixer configured to provide a third output clock signal based, at least in part, on the first input clock signal and the third delayed clock signal;
- and
- a second buffer configured to provide a fourth output clock signal based, at least in part, on the fourth delayed clock signal.
A method comprising:
- delaying a first input clock signal to provide first and second delayed clock signals;
- delaying a second input clock signal to provide third and fourth delayed clock signals;
- providing a first output clock signal based, at least in part, on the first delayed clock signal;
- providing a second output clock signal based, at least in part, on the second input clock signal and the second delayed clock signal;
- providing a third output clock signal based, at least in part, on the first input clock signal and the third delayed clock signal;
- providing a fourth output clock signal based, at least in part, on the fourth delayed clock signal
Dependencies are inferred from the claim text.