US 2018/0123573 A1 · ADJUSTABLE DELAY CIRCUIT FOR OPTIMIZING TIMING MARGIN

Abstract

The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.

Claims20

Dependent claims

An apparatus, comprising:

a signal line supplied with a signal;
an output circuit;
and
a plurality of delay circuits each including an input node, an output node and a same number of transistors between the input node and the output node, and wherein a selected one of the plurality of delay circuits being connected at its input node to the signal line and at its output node to the output circuit with any of the input and output nodes of any one of the rest of the plurality of delay circuits being disconnected from any one of the signal line and the output circuit.

1 more element

Dependencies are inferred from the claim text.

Adjustable delay circuit for optimizing timing margin

Life of this patent

Adjustable delay circuit for optimizing timing margin

Life of this patent

Abstract

Claims20