Semi-data gated flop with low clock power/low internal power with minimal area overhead
AssigneeQUALCOMM Incorporated
InventorsSeid Hadi Rasouli, Xiangdong Chen, Venugopal Boynapalli
Life of this patent
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Abstract
Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values or both the input signal and the output signal have a logic value of zero. The method also includes gating the clock signal if both the input signal and the output signal have a logic value of one.
Claims22
A clock-gating device, comprising:
- a logic device configured to receive an input signal of a flip-flop and an output signal of the flip-flop, and to output an enable signal based on the input signal and the output signal, wherein the enable signal has a first logic value if the input signal and the output signal have different logic values, the enable signal has the first logic value if both the input signal and the output signal have a logic value of zero, and the enable signal has a second logic value if both the input signal and the output signal have a logic value of one;
- and
- a gate device configured to receive the enable signal, to pass a clock signal to an input of a gate in the flip-flop if the enable signal has the first logic value, and to gate the clock signal if the enable signal has the second logic value.
A method for clock gating, comprising:
- receiving an input signal of a flip-flop and an output signal of the flip-flop;
- passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values;
- passing the clock signal to the input of the gate in the flip-flop if both the input signal and the output signal have a logic value of zero;
- and
- gating the clock signal if both the input signal and the output signal have a logic value of one.
A system, comprising:
- a flip-flop comprising:
- a first NOR gate having a first input, a second input, and an output;
- and
- a second NOR gate having a first input, a second input coupled to the output of the first NOR gate, and an output coupled to the second input of the first NOR gate;
- and
- a clock-gating device comprising:
- a logic device configured to receive an input signal of the flip-flop and an output signal of the flip-flop, and to output an enable signal based on the input signal and the output signal, wherein the enable signal has a first logic value if the input signal and the output signal have different logic values, the enable signal has the first logic value if both the input signal and the output signal have a logic value of zero, and the enable signal has a second logic value if both the input signal and the output signal have a logic value of one;
- and
- a gate device configured to receive the enable signal, to pass a clock signal to the first input of the first NOR gate if the enable signal has the first logic value, and to gate the clock signal if the enable signal has the second logic value.
Dependencies are inferred from the claim text.