Inverter switching devices with common source inductance layout to avoid shoot-through

A power converter comprising:

• a DC link with positive and negative buses configured to receive a DC supply voltage;
• a phase leg comprising an upper transistor and a lower transistor coupled in series between the buses and an upper commutation diode and a lower commutation diode coupled across respective collector and emitter terminals of the respective upper and lower transistors, wherein a junction between the upper and lower transistors is configured to be coupled to a load, wherein the upper gate and emitter terminals are arranged to create an upper common source inductance, wherein the lower gate and emitter terminals are arranged to create a lower common source inductance, wherein the upper diode is coupled substantially in parallel with the upper common source inductance, and wherein the lower diode is coupled substantially in parallel with the lower common source inductance;
• and
• a gate driver coupled to the phase leg activating the upper transistor according to an upper gate signal and activating the lower transistor according to a lower gate signal.

A power converter comprising:

• a DC link with positive and negative buses configured to receive a DC supply voltage;
• a phase leg comprising an upper transistor and a lower transistor coupled in series between the buses and an upper diode and a lower diode coupled across respective collector and emitter terminals of the respective upper and lower transistors, wherein a junction between the upper and lower transistors is configured to be coupled to a load, wherein the upper gate and emitter terminals are arranged to create an upper common source inductance, wherein the lower gate and emitter terminals are arranged to create a lower common source inductance, wherein the upper diode is coupled substantially in parallel with the upper common source inductance, and wherein the lower diode is coupled substantially in parallel with the lower common source inductance;
• and
• a gate driver coupled to the phase leg activating the upper transistor according to an upper gate signal and activating the lower transistor according to a lower gate signal;
• wherein the phase leg further comprises a power module substrate carrying a plurality of conductive layers, wherein the conductive layers define a positive rail and a negative rail arranged between first and second mounting regions;
• wherein the upper transistor and the lower diode are mounted to the substrate in the first mounting region;
• and
• wherein the lower transistor and the upper diode are mounted to the substrate in the second mounting region.