Well-based vertical hall element with enhanced magnetic sensitivity

An integrated circuit (IC) chip comprising:

• a substrate having a top surface and a first conductivity type;
• a well region formed in the substrate, the well region doped with a first dopant of a second conductivity type that is opposite the first conductivity type and having a first doping concentration that decreases with an increasing distance from the top surface of the substrate;
• a buried region formed under and in contact with the well region, the buried region doped with a second dopant of the second conductivity type and having a second doping concentration that increases with increasing distance from the well region;
• first, second and third contacts formed on the well region, the first and second contacts defining a first conductive path through the well region, the second and third contacts defining a second conductive path through the well region;
• a fourth contact formed on the well region between the first and second contacts;
• and
• a fifth contact formed on the well region between the second and third contacts.

A vertical Hall element comprising:

• a substrate having a top surface and a first conductivity type;
• a well region formed in the substrate, the well region being doped with a first dopant of a second conductivity type that is opposite the first conductivity type and having a first doping concentration that decreases with an increasing distance from the top surface of the substrate;
• a buried region formed under and in contact with the well region, the buried region being doped with a second dopant of the second conductivity type and having a second doping concentration that increases with an increasing distance from the well region;
• first, second and third contacts formed on the well region, the first and second contacts defining a first conductive path through the well region, the second and third contacts defining a second conductive path through the well region;
• a fourth contact formed on the well region between the first and second contacts;
• and
• a fifth contact formed on the well region between the second and third contacts.

An integrated circuit (IC) chip comprising:

• a substrate having a top surface and a first conductivity type;
• a well region formed in the substrate, the well region doped with a first dopant of a second conductivity type that is opposite the first conductivity type and having a first doping concentration that decreases with an increasing distance from the top surface of the substrate;
• a buried region formed under and in contact with the well region, the buried region doped with a second dopant of the second conductivity type and having a second doping concentration that increases with increasing distance from the well region;
• a first group of contacts formed in the well region;
• a second group of contacts formed in the well region;
• a biasing circuit electrically coupled to the first group of contacts;
• and
• a voltage detector electrically coupled to the second group of contacts.