Semiconductor Structure with Stress-Reducing Buffer Structure

An optoelectronic device comprising:

• a buffer structure including:
• a buffer layer, wherein the buffer layer has a first side including a plurality of islands and a second side opposite the first side at which the islands are coalesced into a single layer, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns;
• and
• an intermediate layer located immediately adjacent to the second side of the buffer layer, wherein the intermediate layer includes a plurality of sub-layers configured to provide stress relief in the optoelectronic device;
• and
• a set of semiconductor layers formed adjacent to the intermediate layer, wherein the buffer structure is configured such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa, wherein the set of semiconductor layers include:
• an n-type layer located on the buffer structure;
• an active region located on a side of the n-type layer opposite the buffer structure;
• and
• a p-type layer located on a side of the active region opposite the n-type layer.

An optoelectronic device comprising:

• a nitride-based buffer structure including:
• a buffer layer, wherein the buffer layer has a first side including a plurality of islands and a second side opposite the first side at which the islands are coalesced into a single layer, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns;
• and
• an intermediate layer located immediately adjacent to the second side of the buffer layer, wherein the intermediate layer comprises a plurality of group III nitride-based sub-layers;
• and
• a set of group III nitride-based semiconductor layers formed adjacent to the intermediate layer, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa, wherein the set of semiconductor layers include:
• a group III nitride-based n-type layer located on the buffer structure;
• a group III nitride-based active region located on a side of the n-type layer opposite the buffer structure, wherein the active region is configured to emit ultraviolet radiation;
• and
• a group III nitride-based p-type layer located on a side of the active region opposite the n-type layer.