Method of Manufacturing Lower Temperature Polycrystal Silicon Thin Film Transistor Array Substrate

A method of manufacturing lower temperature polycrystal silicon thin film transistor array substrate, comprising:

• A) defining a heavily doped region of a source electrode of an N-channel area, a lightly doped region of the source electrode of the N-channel area, a heavily doped region of a drain electrode of the N-channel area and a lightly doped region of the drain electrode of the N-channel area by using a first stripped photomask;
• B) defining a doped region of a source electrode of a P-channel area and a doped region of a drain electrode of the P-channel area by using a second stripped photomask;
• C) defining a pixel region, a contact hole region at the heavily doped region of the drain electrode of the N-channel area, a contact hole region at the heavily doped region of the source electrode of the N-channel area, a contact hole region at the heavily doped region of the drain electrode of the P-channel area, and a contact hole region at the heavily doped region of the source electrode of the P-channel area by using a third stripped photomask;
• and
• D) defining a metal electrode region at the heavily doped region of the drain electrode of the N-channel area, a metal electrode region at the heavily doped region of the source electrode of the N-channel area, a metal electrode region at the heavily doped region of the drain electrode of the P-channel area, and a metal electrode region at the heavily doped region of the source electrode of the P-channel area by using a fourth stripped photomask.