Semiconductor device and method for manufacturing same

A method for manufacturing a semiconductor device which includes at least one thin film transistor on a substrate, the method comprising:

• (a) forming, on a substrate, an island-like semiconductor layer which includes a channel region and a low-concentration impurity region that contains a first conductivity type impurity at a concentration higher than in the channel region, a gate insulating layer covering the semiconductor layer, and a gate electrode on the gate insulating layer;
• (b) forming an interlayer insulating layer on the gate insulating layer and the gate electrode;
• (c) forming a mask on the interlayer insulating layer, and simultaneously etching the gate insulating layer and the interlayer insulating layer using the mask, thereby forming a contact hole in the gate insulating layer and the interlayer insulating layer such that a part of the low-concentration impurity region is exposed through the contact hole;
• (d) implanting a first conductivity type impurity into the part of the low-concentration impurity region of the semiconductor layer via the contact hole, thereby forming a high-concentration impurity region;
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• (e) forming an electrode on the interlayer insulating layer and in the contact hole so as to be in contact with the high-concentration impurity region.

A method for manufacturing a semiconductor device which includes at least a first thin film transistor and a second thin film transistor on a substrate, the method comprising:

• (a) forming, on a substrate, a first semiconductor layer which is to be an active layer of the first thin film transistor and a second semiconductor layer which is to be an active layer of the second thin film transistor, and forming a gate insulating layer so as to cover the first and second semiconductor layers;
• (b) implanting a first conductivity type impurity into a part of the first semiconductor layer and a part of the second semiconductor layer as a first implantation step;
• (c) forming a first gate electrode on a part of the region of the first semiconductor layer in which the impurity is implanted in the first implantation step and a part of the first semiconductor layer which is to be a channel region, and forming a second gate electrode on a part of a region of the second semiconductor layer in which the impurity is not implanted in the first implantation step;
• (d) implanting a first conductivity type impurity into the first and second semiconductor layers using the first and second gate electrodes as masks, as a second implantation step, so that a region of the first semiconductor layer in which the impurity is implanted in both the first and second implantation steps is a first low-concentration impurity region, another region of the first semiconductor layer in which the impurity is implanted in the first implantation step and in which the impurity is not implanted in the second implantation step due to the second gate electrode covering that portion is a second low-concentration impurity region, a region of the second semiconductor layer in which the impurity is implanted in both the first and second implantation steps is a third low-concentration impurity region, and another region of the second semiconductor layer in which the impurity is implanted in the second implantation step but the impurity is not implanted in the first implantation step is a fourth low-concentration impurity region;
• (e) forming an interlayer insulating layer on the gate insulating layer, the first gate electrode and the second gate electrode;
• (f) forming a mask on the interlayer insulating layer, and simultaneously etching the gate insulating layer and the interlayer insulating layer using the mask, thereby forming, in the gate insulating layer and the interlayer insulating layer, a first contact hole through which a part of the first low-concentration impurity region is exposed and a second contact hole through which a part of the third low-concentration impurity region is exposed;
• (g) implanting a first conductivity type impurity into the parts of the first and third low-concentration impurity regions via the first and second contact holes, thereby forming a first high-concentration impurity region in the first semiconductor layer and a second high-concentration impurity region in the second semiconductor layer;
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• (h) forming a first electrode on the interlayer insulating layer and in the first contact hole so as to be in contact with the first high-concentration impurity region, and forming a second electrode on the interlayer insulating layer and in the second contact hole so as to be in contact with the second high-concentration impurity region.