Wrap Around Silicide for FinFETs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Chi-Wen Liu, Ying-Keung Leung
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Abstract
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
Claims20
A method comprising:
- forming a gate stack on a first portion of a semiconductor fin, wherein the semiconductor fin overlaps a semiconductor strip;
- forming template dielectric regions on opposite sides of a second portion of the semiconductor fin, wherein the template dielectric regions have substantially vertical sidewalls;
- forming a recess between the template dielectric regions, wherein the forming the recess comprises etching a top portion of the second portion of the semiconductor fin;
- and
- epitaxially growing a source/drain region in the recess, wherein the source/drain region has substantially vertical sidewalls, and is wider than respective underlying portion of the semiconductor strip.
A method comprising:
- forming a gate stack on a first portion of a semiconductor fin, wherein the semiconductor fin overlaps a semiconductor strip;
- epitaxially growing a source/drain region in template dielectric regions, wherein the source/drain region is grown starting from the semiconductor strip, and the source/drain region has substantially vertical sidewalls parallel to substantially vertical sidewalls of the semiconductor strip, and the source/drain region is wider than the semiconductor strip;
- and
- siliciding portions of the source/drain region.
A method comprising:
- forming a gate stack on a first portion of a semiconductor fin;
- forming a first gate spacer on a sidewall of the gate stack, wherein the first gate spacer is formed as a conformal layer;
- depositing a template dielectric region, with both a second portion of the semiconductor fin and the first gate spacer being embedded in the template dielectric region;
- etching a top portion of the first gate spacer and the second portion of the semiconductor fin to form a recess in the template dielectric region;
- and
- epitaxially growing a source/drain region in the recess.
Dependencies are inferred from the claim text.