Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
Life of this patent
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Abstract
A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.
Claims20
A method of fabricating a vertical fin field effect transistor with a merged top source/drain, comprising:
- forming a plurality of vertical fins on a source/drain layer;
- forming protective spacers on each of the plurality of vertical fins;
- forming a sacrificial plug between two protective spacers;
- forming a filler layer on the protective spacers not in contact with the sacrificial plug;
- selectively removing the sacrificial plug;
- and
- forming an isolation region trench through the source/drain layer into the substrate, wherein the isolation region trench is offset from an adjacent vertical fin by a thickness of one of the protective spacers.
A method of fabricating two vertical fin field effect transistors electrically coupled through a merged top source/drain, comprising:
- forming at least four vertical fins on a source/drain layer;
- forming an isolation region through the source/drain layer to separate the source/drain layer into a first bottom source/drain and a second bottom source/drain, wherein at least two of the least four vertical fins are on the first bottom source/drain, and at least two of the least four vertical fins are on the second bottom source/drain, wherein a first vertical fin on the first bottom source/drain and an adjacent second vertical fin on the second bottom source/drain of the at least four vertical fins are separated by a distance, D1, and the first vertical fin and an adjacent third vertical fin on the first bottom source/drain are separated by a distance, D2, wherein D2 is greater than D1.;
- and
- forming a top source/drain on each of the at least four vertical fins, wherein the top source/drains are formed to a size that is sufficient for the top source/drain on the first vertical fin to coalesce into the merged source/drain with the top source/drain on the adjacent second vertical fin.
A method of fabricating two vertical fin field effect transistors electrically coupled through a merged top source/drain, comprising:
- forming an isolation region through a source/drain layer on a substrate to separate the source/drain layer into a first bottom source/drain and a second bottom source/drain;
- forming three vertical fins on the first bottom source/drain and three vertical fins on the second bottom source/drain;
- removing a middle vertical fin of the three vertical fins on the first bottom source/drain, wherein a first vertical fin remaining on the first bottom source/drain and a second vertical fin remaining on the first bottom source/drain are separated by a distance, D2;
- removing a middle vertical fin of the three vertical fins on the second bottom source/drain, wherein a third vertical fin remaining on the second bottom source/drain and a fourth vertical fin remaining on the second bottom source/drain are separated by a distance, D2, and the second vertical fin and the third vertical fin are separated by a distance, D1, wherein D2 is greater than D1.;
- and
- forming a top source/drain on each of the remaining four vertical fins, wherein the top source/drains are formed to a size that is sufficient for the top source/drain on the second vertical fin and the third vertical fin to coalesce into the merged top source/drain.
Dependencies are inferred from the claim text.