Vtfet devices utilizing low temperature selective epitaxy

A method for forming a semiconductor structure comprising:

• providing a substrate comprising a first surface comprising single crystalline silicon and at least one additional surface comprising a dielectric material;
• epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on the substrate to form a single crystalline silicon on the first surface and a polysilicon/amorphous silicon on the additional surface;
• and
• exposing the epitaxially grown silicon layer to an etchant comprising HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface,
• wherein the growing of the silicon layer with the dopant and the exposing of the grown silicon layer to the etchant is cycled, wherein multiple layers of the germanium diffused region is formed in and on the single crystalline silicon formed on the first surface.

A method for forming a semiconductor structure comprising:

• providing a substrate comprising a first surface comprising single crystalline silicon and at least one additional surface comprising a dielectric material;
• epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on the substrate to form a single crystalline silicon on the first surface and a polysilicon/amorphous silicon on the additional surface;
• and
• exposing the epitaxially grown silicon layer to an etchant comprising HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface, wherein the first surface is an exposed top surface of a vertically oriented channel region of a vertical finFET structure.