High voltage semiconductor devices and methods of making the devices

A multi-cell MOSFET device comprising:

• an n-type drift layer on an n-type substrate;
• a plurality of MOSFET cells, each of the MOSFET cells comprising:
• first and second p-type well regions in spaced relation on the n-type drift layer;
• an n-type JFET region on the n-type drift layer between the first and second p-type well regions, wherein each of the first and second p-type well regions has a channel region adjacent the JFET region;
• first and second n-type source regions on each of the first and second p-type well regions and adjacent the channel regions opposite the JFET region, wherein the first and second n-type source regions have a higher dopant concentration than the n-type drift layer;
• source ohmic contacts on each of the first and second n-type source regions;
• a gate dielectric layer on the JFET region and channel regions;
• a gate layer on the gate dielectric layer;
• an interlayer dielectric layer on the gate layer;
• and
• first and second p-type body contact regions on the n-type drift layer and adjacent the first and second n-type source regions opposite the channel regions, wherein the first and second p-type body contact regions have a higher dopant concentration than the first and second p-type well regions;
• one or more n-type Schottky regions on the n-type drift layer adjacent one or more of the MOSFET cells;
• and
• a source metal layer on and in contact with the source ohmic contacts;
• a Schottky metal layer on and in contact with the one or more n-type Schottky regions, the Schottky metal layer forming a Schottky contact with the one or more n-type Schottky regions.