Method and structure for forming mosfet with reduced parasitic capacitance
AssigneeInternational Business Machines Corporation
InventorsKangguo CHENG, Peng XU, Chen ZHANG
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Abstract
A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.
Claims17
A method of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), said method comprising:
- on a gate structure coated with a high-k sidewall spacer film, etching off said high-k sidewall spacer film from a top surface of said gate structure and from a portion of vertical walls of said gate structure;
- and
- replacing said etched-off high-k sidewall spacer film on said vertical walls with an ultra low-k material.
A finFET (Field Effect Transistor) comprising:
- a gate structure comprising a gate contact covering a high impedance film layer;
- a fin channel directly under said gate structure such that a movement of carriers is controlled by a voltage in said gate metal contact;
- a source epitaxial region covered by a source contact metal layer, adjacent to a first side of said gate structure;
- and
- a drain epitaxial region covered by a drain contact metal layer, adjacent to a second side of said gate structure and opposing said first side,
- wherein said gate structure further comprises a gate sidewall spacer layer to isolate said gate from said source contact metal layer and said drain contact metal layer, and
- wherein said gate sidewall spacer layer comprises a portion between said gate structure and said drain contact metal layer and between said gate structure and said source contact metal layer with a material having an ultra low-k material.
The MOSFET of claim 16, wherein said gate sidewall spacer layer comprises a portion comprising an air spacer between said gate structure and said source epitaxial region and between said gate structure and said drain epitaxial region.
The MOSFET of claim 16, wherein said high-k sidewall spacer film comprises a SiBCN (Silicon-Boron-Carbon-Nitride) thin film.
Dependencies are inferred from the claim text.