US 2018/0122905 A1Published application

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

AssigneeSanDisk Technologies LLC

InventorsHiroyuki Ogawa, Yasuo Kasagi, Satoshi Shimizu, Kazuyo Matsumoto, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai

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Abstract

Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

Claims20

Dependent claims

A three-dimensional memory device comprising:

a source semiconductor layer having a thickness modulation and located over a substrate and including a recess region;
source strap material portions located over the source semiconductor layer, and the recess region is filled by a same semiconductor material as the source strap material portions;
a vertically alternating stack of electrically conductive layers and insulating layers located over the source strap material portions;
an array of memory stack structures that extend through the vertically alternating stack and into an upper portion of the source semiconductor layer, each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel and including an opening through which a respective one of the source strap material portions contacts the semiconductor channel;
an insulating wall structure vertically extending through the vertical alternating stack and laterally extending along a same direction as the recess region and protruding downward into portions of the source strap material portions;
and
a cap semiconductor layer overlying the source strap material portions and underlying the vertically alternating stack, contacting top surfaces of the source strap material portions, and not contacting, and laterally spaced from, sidewalls of the insulating wall structure by a bottommost insulating layer within the vertically alternating stack.

4 more elements

A three-dimensional memory device comprising:

a source semiconductor layer having a thickness modulation and located over a substrate and including a recess region;
source strap material portions located over the source semiconductor layer, and the recess region is filled by a same semiconductor material as the source strap material portions;
a vertically alternating stack of electrically conductive layers and insulating layers located over the source strap material portions;
an array of memory stack structures that extend through the vertically alternating stack and into an upper portion of the source semiconductor layer, each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel and including an opening through which a respective one of the source strap material portions contacts the semiconductor channel;
an insulating wall structure vertically extending through the vertical alternating stack and laterally extending along a same direction as the recess region and protruding downward into portions of the source strap material portions;
and
a cap semiconductor layer overlying the source strap material portions and underlying the vertically alternating stack and contacting top surfaces of the source strap material portions;
dielectric material portions located at a same level as the source strap material portions;
and
at least one patterned dielectric liner that overlies the dielectric material portions and underlying the cap semiconductor layer.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/458,269Filed 14 Mar 2017
Priority: 3 Nov 2016
Published: 3 May 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 62/292
Of igfets: non-planar channels of IGFETs
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10B 41/41
Characterised by the peripheral circuit region: of a memory region comprising a cell select transistor, e.g. NAND