Integration methods to fabricate internal spacers for nanowire devices

An integrated circuit structure, comprising:

• a nanowire stack above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires;
• a gate structure comprising a gate dielectric and a gate electrode, the gate structure wrapped around each of the plurality of nanowires, the gate structure having a first sidewall and a second sidewall opposite the first sidewall, the gate structure having a portion above the nanowire stack;
• a channel region in the plurality of nanowires surrounded by the gate structure;
• a first external sidewall spacer adjacent to the first sidewall of the portion of the gate structure above the nanowire stack;
• a second external sidewall spacer adjacent to the second sidewall of the portion of the gate structure above the nanowire stack;
• a first source or drain region on a first side of the channel region;
• a second source or drain region on a second side of the channel region opposite the first side;
• a first internal insulative spacer adjacent to a portion of the first sidewall of the gate structure between nanowires of the nanowire stack, the first internal insulative spacer beneath the first external gate sidewall spacer, the first internal insulative spacer between and in contact with both of the gate dielectric and the first source or drain region;
• and
• a second internal insulative spacer adjacent to a portion of the second sidewall of the gate structure between nanowires of the nanowire stack, the second internal insulative spacer beneath the second external gate sidewall spacer, the second internal insulative spacer between and in contact with both of the gate dielectric and the second source or drain region.