High-k metal-insulator-metal capacitor and method of manufacturing the same

A semiconductor device comprising at least one metal-insulator-metal (MIM) capacitor constructed in a plurality of successive layers of a back-end-of-line (BEOL) layers in said semiconductor device, said MIM capacitor comprising:

• a lower metal fill region formed to fill a cavity of a lower BEOL layer, the lower metal fill region serving as a bottom electrode contact for the MIM capacitor;
• an upper metal fill region formed to fill a cavity of an upper BEOL layer, the upper metal region serving as a top electrode contact for the MIM capacitor;
• and
• a core electrode structure formed to fill a cavity in at least one intermediate BEOL layer between the lower and upper BEOL layers, the core electrode structure comprising:
• a center metal fill region formed to fill a center of the cavity, to serve as a principle upper electrode plate for the MIM capacitor, the center metal fill region electrically connected to a bottom surface of the upper metal fill region formed in the upper BEOL layer;
• a layer of high-k dielectric material continuously surrounding the center metal fill region on side and bottom surfaces of the center metal fill region, the high-k dielectric material layer serving as a plate separation dielectric for the MIM capacitor;
• and
• a layer of liner metal lining sidewall surfaces of the cavity in the at least one intermediate BEOL layer, the layer of liner metal contacting an outer surface of the layer of high-k dielectric material, the layer of liner metal serving as a principle lower electrode plate for the MIM capacitor, the layer of liner metal electrically connected to a top surface of the lower metal fill region formed in the lower BEOL layer.

A method of fabricating a metal-insulator-metal (MIM) capacitor, said method comprising:

• post patterning an insulation layer for an etch;
• using the post patterning as an etch mask, etching through the insulation layer to create a cavity that exposes a top surface of an underlying metal region, the exposed underlying metal region providing a lower contact for a lower electrode of the metal-insulator-metal (MIM) capacitor;
• using the post patterning as a mask and depositing a layer of liner metal on sidewall and bottom surfaces of the cavity, the layer of liner material contacting a top surface of the underlying metal region, the layer of liner material serving as a lower electrode plate for the MIM capacitor;
• using the post patterning as a mask and depositing a layer of low-k dielectric material, the layer of low-k dielectric material serving as a dielectric layer between the lower electrode plate and an upper electrode plate of the MIM capacitor;
• and
• using the post patterning as a mask and depositing, on a top surface of the low-k dielectric material, a layer of fill metal to provide a fill metal region serving as an upper electrode plate for the MIM capacitor that opposes the layer of liner material serving as the lower electrode plate for the MIM capacitor.