Low Noise InGaAs Photodiode Array
AssigneePrinceton Infrared Technologies, Inc.
InventorMartin H. Ettenberg
Life of this patent
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Abstract
A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.
Claims15
A method of forming a focal plane detector array structure for detecting visible and shortwave infrared light, the method comprising:
- forming a multilayer semiconductor detector array structure comprising at least one cap layer which is at least partially composed of indium and at least one InxGa1−xAs semiconductor layer;
- forming a buried photodiode by
- doping, with a p-type dopant, a p-type region of the multilayer semiconductor detector array structure such that the p-type region extends from a surface of multilayer semiconductor array structure to the at least one InxGa1−xAs semiconductor layer;
- and
- doping, with an n-type dopant, an n-type region on the surface of the multilayer semiconductor array structure such that the p-type region is completely covered by the n-type region;
- forming an electrical switch internal to the multilayer structure to remove charge from buried photodiode by
- forming a gate contact that contacts the at least one cap layer;
- and
- doping a second p-type region to form a drain, wherein charge flows from the buried photodiode to the drain when no voltage is applied to the gate contact;
- and
- hybridizing the multilayer semiconductor detector array structure to a read out integrated circuit (ROTC) comprising an amplification and storage circuit that also controls the flow of charge from the buried photodiode, wherein the buried photodiode is connected to the amplification and storage circuit by the electrical switch internal to the multilayer structure.
A focal plane array comprising:
- a photodiode array that includes a plurality pixels, wherein each of the plurality of pixels includes a multilayer semiconductor detector array structure comprising:
- at least one cap layer which is at least partially composed of indium;
- at least one InxGa1−xAs semiconductor layer;
- a buried photodiode, comprising;
- a p-type doped region that extends from a surface of the multilayer semiconductor detector array structure through the at least one cap layer to the InxGa1−xAs layer;
- and
- an n-type doped region that extends from the surface of the multilayer semiconductor detector array structure to the at least one cap layer and that completely covers the p-type region;
- a first junction field effect transistor (JFET) comprising a gate and a drain proximate to the buried photodiode, wherein the first JFET 15 internal to the multilayer semiconductor detector array structure and controls charge flow from the buried photodiode to the amplification and storage circuit;
- and
- a second JFET comprising a gate and a drain proximate to the first JFET, wherein the second JFET is internal to the multilayer semiconductor detector array structure and controls charge flow from the drain of the first JFET to the drain of the second JFET;
- and
- a read out integrated circuit (ROIC) including an amplification and storage circuit, wherein ROIC is hybridized to the photodiode array, and wherein the ROIC has circuitry that is capable of controlling the gate voltages of gates of the first and second JFETs to control charge flow from buried photodiode through at least one of the first and second JFETs to the amplification and storage circuit.
Dependencies are inferred from the claim text.