Selective deposition and planarization for a cmos image sensor

A method for manufacturing a contact image sensor, the method comprising:

• forming a passivation layer over a semiconductor substrate;
• forming a scribe line opening through the passivation layer and the semiconductor substrate, the scribe line opening overlying and exposing a metal line of a back end of line (BEOL) metallization stack;
• forming a conductive pad within the scribe line opening, which electrically contacts the BEOL metallization stack;
• forming a first dielectric layer within the scribe line opening over the conductive pad by a selective deposition process, wherein the first dielectric layer is formed on the conductive pad at a deposition rate greater than depositing on the passivation layer;
• forming a second dielectric layer on the first dielectric layer;
• performing a chemical mechanical polish (CMP) into the second dielectric layer;
• and
• performing a wet etch process into the second dielectric layer or the first dielectric layer to etch back an upper surface of the first or second dielectric layer to be substantially planar.

A method for manufacturing a contact image sensor, the method comprising:

• forming a passivation layer over a semiconductor substrate on a light-receiving side of the contact image sensor;
• forming a scribe line opening through the passivation layer and the semiconductor substrate, the scribe line opening overlying and exposing a metal line of a back end of line (BEOL) metallization stack;
• forming a conductive pad within the scribe line opening, the conductive pad comprising a base region and a protruding region, the protruding region protruding from the base region into the BEOL metallization stack;
• and
• forming a first dielectric layer within the scribe line opening over the conductive pad and extending over the passivation layer, wherein the first dielectric layer has a concave upper surface directly above the conductive pad;
• and
• forming a second dielectric layer on the concave upper surface of the first dielectric layer, the second dielectric layer having an upper surface being substantially aligned with an upper surface of the first dielectric layer directly above the passivation layer.