Ltps array substrate and method for producing the same

A low temperature poly-silicon (LTPS) array substrate, comprising:

• a substrate;
• a gate, which is disposed on the substrate;
• a first insulating layer, a polycrystalline silicon layer, and a second insulating layer, which are sequentially disposed on the gate, wherein the second insulating layer comprises first contact holes formed therein;
• a source and a drain, which are disposed on the second insulating layer so that the source and the drain are electrically connected to the polycrystalline silicon layer via the first contact holes, respectively;
• a passivation layer, which is disposed on the source, the drain, and the second insulating layer, wherein the passivation layer comprises a second contact hole formed therein to expose a surface of the drain;
• a third insulating layer, which is disposed on the passivation layer in such a way that the second contact hole is exposed outside the third insulating layer;
• and
• a pixel electrode, which is disposed on the third insulation layer and is electrically connected to the drain via the second contact hole.