Ltps array substrate and manufactoring method thereof

A low temperature poly-silicon (LTPS) array substrate, comprising:

• a substrate;
• a source electrode and a drain electrode, which are arranged on the substrate;
• a poly-silicon layer, which is arranged on the substrate including the source electrode and the drain electrode, wherein the poly-silicon layer partially covers the source electrode and the drain electrode;
• an insulating layer, which is arranged on the poly-silicon layer and the source and drain electrodes, wherein the insulating layer is formed through passivation of a part of the poly-silicon layer that covers the substrate including the source electrode and the drain electrode;
• a gate electrode, which is arranged on the insulating layer between the source electrode and the drain electrode, wherein the source and drain electrodes, the poly-silicon layer, and the gate electrode collectively form a thin-film transistor (TFT);
• a planar layer, which is arranged on the substrate including the gate electrode, wherein the planar layer is formed with a contact hole extending therethrough to expose a surface of the drain electrode;
• a common electrode, which is arranged on the planar layer except the TFT of the LTPS array substrate;
• a passivation layer, which is arranged on the planar layer and the common electrode layer, such that the passivation layer does not cover the contact hole;
• a pixel electrode, which is arranged on the passivation layer, wherein the pixel electrode is electrically connected with the drain electrode through the contact hole.