Vertical memory devices and methods of manufacturing the same

A vertical memory device, comprising:

• a first structure including:
• a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, a diffusion prevention pattern, and a second undoped semiconductor pattern sequentially stacked, the doped semiconductor pattern including a silicon pattern doped with p-type impurities, and the diffusion prevention pattern including a silicon pattern doped with carbon and the p-type impurities, and
• an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure;
• and
• a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.

A vertical memory device, comprising:

• a lower semiconductor pattern structure filling a recess on a substrate and protruding above an upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, only the doped semiconductor pattern including impurities among the first undoped semiconductor pattern, the doped semiconductor pattern, and the second undoped semiconductor pattern;
• an upper semiconductor pattern on the lower semiconductor pattern structure;
• and
• a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.