Fabrication of vertical fin field effect transistors having top air spacers and a self-aligned top junction
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
Life of this patent
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Abstract
A method of fabricating adjacent vertical fins with top source/drains having an air spacer and a self-aligned top junction, including, forming two or more vertical fins on a bottom source/drain, forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the adjacent vertical fins, and forming a source/drain liner on the top source/drains, where the source/drain liner occludes the gap between adjacent top source/drains to form a void space between adjacent vertical fins.
Claims15
A method of fabricating a semiconductor structure, comprising:
- forming two or more vertical fins on a bottom source/drain, wherein at least two of the two or more vertical fins are adjacent;
- forming a bottom spacer layer on the bottom source/drain layer;
- forming a fill layer on the bottom spacer layer;
- forming a top spacer layer on the fill layer;
- forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the top source/drains on each pair of adjacent vertical fins;
- forming a source/drain liner on the top source/drains, wherein the source/drain liner occludes the gap between the top source/drains on each pair of adjacent vertical fins to form a void space between each pair of adjacent vertical fins;
- and
- forming an interlayer dielectric on the source/drain liner, where the interlayer dielectric does not fill in the void space between each pair of adjacent vertical fins.
A method of fabricating a plurality of vertical fin field effect transistors, comprising:
- forming a bottom source/drain layer at a surface of a substrate;
- forming four or more vertical fins on the bottom source/drain layer;
- forming a bottom spacer layer on the bottom source/drain layer;
- forming a gate structure on each of the plurality of vertical fins;
- forming a fill layer on the bottom spacer layer and the gate structure on each of the plurality of vertical fins;
- forming a top spacer layer on the fill layer and the gate structures;
- forming a first set of top source/drains on at least two, but at least two fewer than all, of the four or more vertical fins, wherein the at least two of the four or more vertical fins are adjacent, and wherein there is a gap between each pair of adjacent top source/drains in the first set;
- forming a masking layer on the first set of top source/drains;
- forming a second set of top source/drains on the at least two fewer than all of the four or more vertical fins, wherein the at least two fewer than all of the four or more vertical fins are adjacent, and wherein there is a gap between each pair of adjacent top source/drains in the second set, and the top source/drains in the first set have a different size than the top source/drains in the second set;
- and
- forming a source/drain liner on the top source/drains in the first set and the top source/drains in the second set.
15-20. (canceled)
Dependencies are inferred from the claim text.