Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming

A method of forming an asymmetric transistor for controlling a memory cell, the method comprising:

• providing a semiconductor substrate including a device channel between a drain and a source, a dielectric layer over the drain and the source, and an opening space within a surrounding spacer within the dielectric layer, and wherein the source operatively couples to the memory cell;
• and
• forming a gate stack within the opening space by:
• forming a gate dielectric layer having a planar upper surface and a uniform thickness extending atop an entirety of the device channel,
• forming a dielectric threshold voltage adjusting element within the opening space, the dielectric threshold voltage adjusting element including:
• a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and
• forming a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer,
• wherein the threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

An asymmetric transistor, comprising:

• a semiconductor substrate including a device channel located between a source and a drain;
• at least one gate stack located atop the device channel and within an opening space of a surrounding spacer, the at least one gate stack including, from bottom to top:
• a gate dielectric layer having a planar upper surface and a uniform thickness extending atop an entirety of the device channel,
• a dielectric threshold voltage adjusting element including:
• a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and
• a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer,
• wherein the sloped dielectric element is thicker adjacent a selected one of the source and the drain than the sloped dielectric element is adjacent the other one of the source and the drain, and a threshold voltage in a region adjacent the selected one of the source and the drain is higher than a threshold voltage in the other one of the source and the drain.