Memory cells including vertical nanowire transistors
AssigneeSynopsys, Inc.
InventorsVictor Moroz, Jamil Kawa, Thu Nguyen
Life of this patent
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Abstract
A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.
Claims35
A circuit, comprising:
- an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including two vertical nanowire transistors in series.
A computer system adapted to process a computer implemented representation of a circuit design, comprising:
- a processor and memory coupled to the processor, the memory storing instructions executable by the processor, including instructions to select cells from a cell library and/or to compile a memory layout using a selected cell;
- the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language;
- and
- at least one entry in the cell library, or the selected cell, comprising a specification of physical structures and timing parameters of an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including two vertical nanowire transistors in series.
A computer program product, comprising:
- a memory device having stored thereon a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the specification being executable by a computer running a placement process to control physical placement of the circuit with other circuits or components or for use by a memory compiler to compile a memory array using the cell, the circuit including:
- an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including two vertical nanowire transistors in series.
Dependencies are inferred from the claim text.