Chip package structure with molding layer

A chip package structure, comprising:

• a first chip, a second chip, and a third chip, wherein the second chip is between the first chip and the third chip;
• a first molding layer surrounding the first chip and the second chip, wherein the first molding layer is a single layer structure;
• and
• a second molding layer surrounding the third chip and the first molding layer, wherein a bottom surface of the first molding layer and a bottom surface of the second molding layer are substantially coplanar.

A chip package structure, comprising:

• a first chip, a second chip, and a third chip, wherein the second chip is between the first chip and the third chip;
• a first molding layer surrounding the first chip;
• a second molding layer surrounding the second chip;
• a third molding layer surrounding the third chip, the first molding layer, and the second molding layer, wherein a bottom surface of the first chip, a bottom surface of the first molding layer, and a bottom surface of the third molding layer are substantially coplanar;
• and
• a wiring structure over the third molding layer and the third chip.