STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S

A memory device comprising:

• a first memory die wherein the first memory die comprises at least two through silicon vias (TSVs), wherein the first memory die has a side, wherein the side of the first memory die has an interface region thereon, wherein the interface region comprises at least two interconnects, and wherein a first interconnect of the at least two interconnects is electrically coupled to a first through silicon via of the at least two through silicon vias (TSVs) and a second interconnect of the at least two interconnects is electrically coupled to a second through silicon via of the at least two through silicon vias (TSVs), and
• a second memory die, wherein the second memory die has a side, wherein the side of the second memory die comprises at least two electrical connection regions, and
• wherein the first memory die is stacked on the second memory die, wherein the first interconnect of the at least two interconnects is coupled to a first electrical connection region of the at least two electrical connection regions of the second memory die, wherein the first through silicon via (TSV) passes through the first memory die in a first direction, wherein the first interconnect provides an off-set between the first electrical connection region of the second memory die and the first through silicon via (TSV) in a second direction, and wherein the first direction is different from the second direction, and wherein the second interconnect of the at least two interconnects is coupled to a second electrical connection region of the at least two electrical connection regions of the second memory die.

A system comprising:

• a processor,
• a wireless connectivity component wherein the wireless connectivity component allows the system to communicate wirelessly with an external device and wherein the processor and the wireless connectivity component are coupled, and
• a memory device wherein the processor and the memory device are coupled and the memory device comprises:
• a first memory die wherein the first memory die comprises at least two through silicon vias (TSVs), wherein the first memory die has a side, wherein the side of the first memory die has an interface region thereon, wherein the interface region comprises at least two interconnects, and wherein a first interconnect of the at least two interconnects is electrically coupled to a first through silicon via of the at least two through silicon vias (TSVs) and a second interconnect of the at least two interconnects is electrically coupled to a second through silicon via of the at least two through silicon vias (TSVs), and
• a second memory die, wherein the second memory die has a side, wherein the side of the second memory die comprises at least two electrical connection regions, and
• wherein the first memory die is stacked on the second memory die, wherein the first interconnect of the at least two interconnects is coupled to a first electrical connection region of the at least two electrical connection regions of the second memory die, wherein the first through silicon via (TSV) passes through the first memory die in a first direction, wherein the first interconnect provides an off-set between the first electrical connection region of the second memory die and the first through silicon via (TSV) in a second direction, and wherein the first direction is different from the second direction, and wherein the second interconnect of the at least two interconnects is coupled to a second electrical connection region of the at least two electrical connection regions of the second memory die.