US 2018/0122772 A1 · SEMICONDUCTOR PACKAGES

Abstract

A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.

Claims23

Dependent claims

A semiconductor device, comprising:

a first package including:
a redistribution substrate,
a first semiconductor chip disposed on the redistribution substrate,
a connection substrate disposed on the redistribution substrate, the connection substrate surrounding the first semiconductor chip in a plan view of the device, and
an inductor structure situated within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate;
and
a second package stacked on the first package,
the second package including at least one outer terminal electrically connected to the first package,
wherein the outer terminal is disposed on a second region of the connection substrate, and
the first region and the second region are spaced apart from each other in the plan view of the device.

7 more elements

A semiconductor package, comprising:

a redistribution substrate including an insulating substrate, and an internal wiring layer of conductive traces extending within the insulating substrate;
a connection substrate disposed on the redistribution substrate, the connection substrate including an insulating member having a bottom surface facing towards the redistribution substrate and a top surface facing away from the redistribution substrate and defining an opening therein extending vertically from the top surface towards the redistribution substrate, at least one inductor embedded within the insulating member, and at least one electrical connector extending vertically through the insulating member to provide an electrically conductive path from the top surface of the insulating member to the redistribution substrate;
and
a semiconductor chip disposed on the redistribution substrate within the opening in the insulating member and electrically connected to the wiring layer of the redistribution substrate,
wherein the connection substrate has at least one first region and at least one second region,
the at least one electrical connector of the connection substrate is confined to the at least one first region of the connection substrate,
the at least one inductor of the connection substrate is confined to the at least one second region of the connection substrate and is electrically connected to the first semiconductor chip through the redistribution substrate, and
each said at least one first region of the connection substrate is laterally spaced from each said at least one second region of the connection substrate in a plan view of the package such that a footprint of the at least one inductor does not overlap a footprint of the at least one electrical connector of the connection substrate.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor packages

Life of this patent

Semiconductor packages

Life of this patent

Abstract

Claims23