IC with Insulating Trench and Related Methods
AssigneeSTMicroelectronics S.r.I.
InventorsAlberto Pagani, Giovanni Girlando, Federico Giovanni Ziglioli, Alessandro Finocchiaro
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Abstract
A method of making an integrated circuit (IC) includes forming circuitry over a top surface of a semiconductor substrate having the top surface and an opposite bottom surface. An antenna is formed in an interconnect layer formed above the semiconductor substrate, where the antenna is coupled to circuitry. A seal ring is formed around a periphery of the interconnect layer. The seal ring is disposed around the antenna and the circuitry. A trench with a solid-state insulating material is formed. The trench extends vertically into the semiconductor substrate and extends laterally across the IC.
Claims21
An semiconductor device comprising:
- a semiconductor substrate comprising a top surface and an opposite bottom surface;
- circuitry disposed at the top surface;
- an interconnect layer disposed over the semiconductor substrate;
- an antenna disposed in the interconnect layer, the antenna being coupled to the circuitry;
- a seal ring disposed around a periphery of the interconnect layer;
- and
- a trench extending from the bottom surface into the semiconductor substrate towards the top surface, the trench comprising a solid-state insulating material, the trench having a tapering sidewall, wherein a width of the trench at the bottom surface is greater than a width of the trench in the semiconductor substrate, wherein the width of the trench at the bottom surface and the width of the trench in the semiconductor substrate are measured along a plane parallel to the bottom surface.
A method of making an integrated circuit (IC) comprising:
- forming circuitry over a top surface of a semiconductor substrate comprising the top surface and an opposite bottom surface;
- forming an antenna in an interconnect layer formed above the semiconductor substrate, the antenna coupled to circuitry;
- forming a seal ring around a periphery of the interconnect layer, the seal ring disposed around the antenna and the circuitry;
- and
- forming a trench comprising a solid-state insulating material, the trench extending vertically into the semiconductor substrate and extending laterally across the IC.
A method of testing a wafer, the method comprising:
- providing the wafer comprising a plurality of integrated circuits (ICs), each of the plurality of ICs comprising:
- circuitry disposed over a top surface of a semiconductor substrate comprising the top surface and an opposite bottom surface,
- an antenna disposed in an interconnect layer, the interconnect layer disposed above the top surface of the semiconductor substrate, the antenna being coupled to circuitry,
- a seal ring disposed around a periphery of the interconnect layer, the seal ring being disposed around the antenna and the circuitry, and
- a trench comprising a solid-state insulating material, the trench extending vertically into the semiconductor substrate and extending laterally across the associated one of the plurality of ICs;
- and
- operating a testing device to direct radio frequency (RF) radiation onto the wafer to be received by the respective antenna of the plurality of ICs.
Dependencies are inferred from the claim text.