Semiconductor wafer, semiconductor package and method for manufacturing the same

A semiconductor package, comprising:

• a substrate structure defining a via;
• a first insulation layer covering a first surface of the substrate structure, wherein the first insulation layer extends into the via, covers a lateral wall of the via and exposes a bottom surface at a bottom of the via;
• a conductive layer covering the first insulation layer and the bottom surface exposed by the first insulation layer;
• and
• a second insulation layer covering the conductive layer, wherein the second insulation layer fills up the via;
• wherein a modulus of elasticity of the first insulation layer and a modulus of elasticity of the second insulation layer are each less than 1.7 GPa.

A method for manufacturing a semiconductor wafer, comprising:

• providing a substrate structure defining a via;
• forming a first insulation layer over a first surface of the substrate structure and extending into the via to cover a lateral wall of the via and expose a bottom surface at a bottom of the via, wherein the first insulation layer comprises a photosensitive material;
• forming a conductive layer over the first insulation layer and the bottom surface exposed by the first insulation layer;
• forming a second insulation layer over the conductive layer, wherein the second insulation layer defines an opening exposing a portion of the conductive layer;
• and
• forming a conductive pad over the second insulation layer, wherein the conductive pad is electrically connected to the conductive layer through the opening of the second insulation layer