Avd hardmask for damascene patterning
AssigneeIntel Corporation
InventorsRuth A. BRAIN, Kevin J. FISCHER, Michael A. CHILDS
Life of this patent
Estimating the term…
Abstract
A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
Claims20
(canceled)
An integrated circuit structure, comprising:
- a first interconnection line above a substrate;
- an interlayer dielectric (ILD) material above the first interconnection line;
- a conductive via in a lower portion of the ILD material, the conductive via on a portion of the first interconnection line, wherein the conductive via has substantially vertical sidewalls spaced apart by a width along a first horizontal direction, and wherein the conductive via has a length along a second horizontal direction orthogonal to the first horizontal direction;
- and
- a second interconnection line in an upper portion of the ILD material, the second interconnection line on the conductive via, the second interconnection line having substantially vertical sidewalls spaced apart by the width along the first horizontal direction, and the second interconnection line having a length along the second horizontal direction greater than the length of the conductive via along the second horizontal direction, wherein the substantially vertical sidewalls of the second interconnection line are continuous with the substantially vertical sidewalls of the conductive via.
An integrated circuit structure, comprising:
- a conductive contact above a substrate;
- a first interlayer dielectric (ILD) material above the conductive contact;
- a conductive via in a lower portion of the first ILD material, the conductive via on a portion of the conductive contact, wherein the conductive via has sidewalls spaced apart by a width along a first horizontal direction at a top of the conductive via, and wherein the conductive via has a length along a second horizontal direction orthogonal to the first horizontal direction;
- an interconnection line in an upper portion of the first ILD material, the interconnection line on the conductive via, the interconnection line having sidewalls spaced apart by the width along the first horizontal direction at a bottom of the interconnection line, and the interconnection line having a length along the second horizontal direction greater than the length of the conductive via along the second horizontal direction;
- a hardmask layer on the upper portion of the first ILD material, the hardmask layer having an opening exposing an upper surface of the interconnection line;
- and
- a second interlayer dielectric (ILD) material on the hardmask layer and on the upper surface of the interconnection line.
Dependencies are inferred from the claim text.