Semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor device, comprising:

• forming a first interlayer dielectric layer over a substrate;
• forming first recesses in the first interlayer dielectric layer;
• forming metal wirings and dummy metal wirings in the first recesses, the metal wirings being part of functioning circuitry and the dummy metal wirings not being part of functioning circuitry;
• forming a mask layer over the metal wirings and the first interlayer dielectric layer;
• forming a first opening over adjacent two metal wirings and a second opening over adjacent two dummy metal wirings by patterning the mask layer;
• forming a first groove corresponding to the first opening and a second groove corresponding to the second opening by etching the first interlayer dielectric layer;
• and
• forming a second interlayer dielectric layer so that a first air gap is formed in the first groove between the adjacent two metal wirings and a second air gap is formed in the second groove between adjacent the two dummy metal wirings, wherein:
• the metal wirings are arranged with a first space or a second space between the metal wirings, the second space having a greater length than the first space,
• no adjacent two metal wirings are arranged with a space smaller than the first space,
• the first air gap has a longer-side length along a first direction and a shorter-side width along a second direction perpendicular to the first direction in plan view,
• the second air gap has a first side length along the first direction and a second-side length along the second direction in plan view, and
• a ratio of the longer-side length and the shorter-side width of the first air gap is greater than a ratio of the first-side length and the second-side length of the second air gap.

A method for designing a layout structure of a semiconductor device by using a computer, the method comprising:

• arranging first air gap patterns over first wiring patterns;
• locating one via from plural vias, each of the plural vias overlapping at least one of first wiring patterns;
• determining whether any first air gap patterns are included in a search area within a search distance from the via;
• if no first air gap pattern is included in the search area, arranging at least one second air gap pattern to partially overlap a first wiring pattern located in the search area;
• and
• outputting photo mask design data in a binary format for the first air gap patterns and the second air gap patterns.