Plug structure of a semiconductor chip and method of manufacturing the same

A method of manufacturing a plug structure of a semiconductor chip, comprising:

• forming a via hole through a semiconductor substrate and an insulating interlayer, wherein the via hole exposes a pad structure, wherein the pad structure is disposed in the insulating interlayer;
• forming an insulating pattern on an inner surface of the via hole, wherein the insulating pattern includes a burying portion that fills a notch, wherein the notch is formed on the semiconductor substrate during the forming of the via hole;
• and
• forming a plug on the insulating pattern and in the via hole, wherein the plug is electrically connected with the pad structure.

A multi-chip package, comprising:

• a first substrate;
• a first semiconductor chip disposed on the first substrate;
• a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip is disposed between the first substrate and the second semiconductor chip;
• and
• first and second conductive bumps,
• wherein the first semiconductor chip includes:
• a second substrate having a first side and a second side opposite to the first side, wherein the first side faces the second semiconductor chip;
• an insulating interlayer disposed on the second side of the second substrate;
• a pad structure disposed in the insulating interlayer, wherein the pad structure faces the first substrate, and the pad structure is electrically connected to the first conductive bump, wherein the first conductive bump is electrically connected to the first substrate;
• a hole extending from the first side of the second substrate, into the second substrate and into the insulating interlayer, to the pad structure, wherein the hole exposes the pad structure, and wherein the hole includes a lateral cavity;
• an insulating pattern disposed in the hole, wherein the insulating pattern includes a first portion and a second portion connected to each other, wherein the first portion fills the lateral cavity, and the second portion covers an interior surface of the hole and exposes the pad structure;
• and
• a plug disposed within the hole, the plug electrically connecting the pad structure with the second conductive bump, wherein the second conductive bump is disposed on the plug and is electrically connected to the second semiconductor chip.