Gate height and spacer uniformity
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
Life of this patent
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Abstract
Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate. A dielectric layer is formed on the substrate and above top surfaces of the first and second sacrificial gates. A self-aligned protection region is formed to cover a first portion of the dielectric layer and a second uncovered portion of the dielectric layer is removed. The first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.
Claims20
A method for forming a semiconductor device, the method comprising:
- forming a sacrificial gate on a substrate;
- forming a dielectric layer comprising a first portion and a second portion on the substrate and above a top surface of the sacrificial gate;
- forming a self-aligned protection region to cover the first portion of the dielectric layer;
- and
- removing the second portion of the dielectric layer to expose a surface of the substrate.
A method for forming a semiconductor device, the method comprising:
- forming a sacrificial gate on a substrate, the sacrificial gate comprising a hard mask, a sidewall spacer, and a self-aligned protection region formed over the sidewall spacer and adjacent to the hard mask;
- and
- removing the hard mask, the self-aligned protection region protecting the sidewall spacer while the hard mask is removed.
Dependencies are inferred from the claim text.