Stacked transistors with different channel widths
AssigneeInternational Business Machines Corporation
InventorsKANGGUO CHENG, LAWRENCE A. CLEVENGER, BALASUBRAMANIAN S. PRANATHARTHIHARAN, JOHN ZHANG
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.
Claims20
A semiconductor device comprising:
- a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire arranged above the second nanowire, the first nanowire connected to a first source/drain region and a second source/drain region;
- a second gate stack arranged about a third nanowire and a fourth nanowire, the third nanowire arranged above the fourth nanowire, the third nanowire connected to a third source/drain region and a fourth source/drain region;
- and
- an insulator layer having a first thickness arranged adjacent to the first gate stack.
A semiconductor device comprising:
- a first stack of nanowires over a substrate;
- a first dielectric layer over the substrate, the first dielectric layer having a first thickness;
- a first source/drain region and a second source/drain region over the first dielectric layer;
- a second stack of nanowires over the substrate;
- a second dielectric layer over the substrate, the second dielectric layer having a second thickness, the second thickness differing from the first thickness;
- and
- a third source/drain region and a fourth source/drain region over the second dielectric layer.
A semiconductor device comprising:
- a first stack of nanowires over a substrate;
- a first source/drain region and a second source/drain region over the substrate, a first number of nanowires in the first stack connecting the first source/drain region to the second source/drain region;
- a second stack of nanowires over the substrate;
- and
- a third source/drain region and a fourth source/drain region over the substrate, a second number of nanowires in the second stack connecting the third source/drain region to the fourth source/drain region, the second number differing from the first number.
Dependencies are inferred from the claim text.