Package structure and manufacturing method thereof

A package structure, comprising:

• a redistribution layer comprising a first surface, a second surface opposite to the first surface, and a patterned circuit layer disposed on the first surface, wherein the patterned circuit layer comprises a plurality of pads, and an outer surface of each of the pads is coplanar with the first surface;
• a chip disposed on the second surface and electrically connected to the patterned circuit layer;
• an encapsulant disposed on the second surface and encapsulating the chip;
• a plurality of under ball release layers disposed on the first surface and respectively covering the pads;
• and
• a plurality of solder balls respectively disposed on the under ball release layers and electrically connected to the pads, wherein an area of a contact surface of each of the under ball release layers, which is in contact with each of the solder balls, is greater than an area of the outer surface of each of the pads.

A manufacturing method of a package structure, comprising:

• forming a release layer on a carrier;
• forming a redistribution layer on the release layer, wherein the redistribution layer comprises a first surface connected to the release layer, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer comprises a plurality of pads disposed on the first surface, and an adhesion between the release layer and the redistribution layer is greater than an adhesion between the release layer and the carrier;
• disposing a chip on the second surface, wherein the chip is electrically connected to the patterned circuit layer;
• forming an encapsulant on the second surface to encapsulate the chip;
• removing the carrier and patterning the release layer to form a plurality of under ball release layers covering the pads;
• and
• forming a plurality of solder balls on the under ball release layers, wherein the solder balls are electrically connected to the pads.