Structure and method to improve fav rie process margin and electromigration
AssigneeInternational Business Machines Corporation
InventorsBenjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
Life of this patent
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Abstract
A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ILD), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
Claims20
A method of forming fully aligned vias in a semiconductor device, the method comprising:
- recessing a first level interconnect line below a first interlevel dielectric (ILD);
- laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess;
- depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric;
- and
- forming a via opening.
A semiconductor device, comprising:
- a first interlevel dielectric (ILD);
- a first level interconnect line embedded in the first interlevel dielectric, the first interconnect line being recessed below the first interlevel dielectric, the first interlevel dielectric including an exposed upper portion bounding the recess;
- a dielectric cap layer deposited on the first interlevel dielectric and the first level interconnect line;
- and
- a second level ILD formed on the first interlevel dielectric and the first level interconnect line.
A semiconductor device, comprising:
- a first interlevel dielectric (ILD);
- a first level interconnect line embedded in the first interlevel dielectric;
- a dielectric layer selectively formed on the first interlevel dielectric and laterally etched to bound a via;
- a dielectric cap layer deposited on the first interlevel dielectric, the via, the first level interconnect line, and the dielectric layer;
- and
- a second level ILD formed on the first interlevel dielectric, the dielectric layer, and the first level interconnect line.
Dependencies are inferred from the claim text.