Test system for measuring propagation delay time of transmission line

A test system comprising:

• a signal generator configured to generate a test signal;
• a plurality of transmission lines including a main line and at least one branch line connected to the main line;
• a plurality of transmission/reception circuits configured to provide the test signal to the transmission lines, the transmission/reception circuits configured to detect a response signal corresponding to the test signal from at least one of the plurality of transmission lines;
• and
• a voltage generator configured to supply a first reference voltage and one of a second reference voltage and a third reference voltage to at least one of the transmission/reception circuits, the second reference voltage being greater than the first reference voltage and the third reference voltage being greater than the first reference voltage and less than the second reference voltage.

A semiconductor test system comprising:

• a tester component configured to supply a first reference voltage, a second reference voltage, and a third reference voltage to at least two transmission/reception circuits, the second reference voltage being greater than the first reference voltage and the third reference voltage being greater than the first reference voltage and less than the second reference voltage;
• the tester component including
• a processor configured to execute machine readable instructions to calculate a first propagation delay time and a second propagation delay time of at least two transmission lines connected to corresponding ones of the at least two transmission/reception circuits;
• the processor configured to
• measure a first time corresponding to a time a first node of the tester component is at the first reference voltage,
• measure a second time corresponding to a time the first node of the tester component is at the second reference voltage,
• measure a third time corresponding to a time a second node of the tester component is at the first reference voltage, and
• measure a fourth time corresponding to a time the second node of the tester component is at the third reference voltage;
• the tester component configured to test at least one device under test on at least one wafer by adjusting first and second output clock signals by an amount corresponding to the first and second propagation delay times.