US 2018/0122646 A1 · LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES

Abstract

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.

Claims20

Dependent claims

A method for forming a semiconductor structure, the method comprising:

forming a structure on a substrate comprising a semiconductor fin, a disposable gate formed in contact with the semiconductor fin, and a spacer in contact with the disposable gate and the semiconductor fin;
epitaxially growing a source region and a drain region within the semiconductor fin;
forming a contact metal layer on and in contact with the source region and the drain region;
and
prior to removing the disposable gate, forming one of a silicide and a germanide on the source region and the drain region from the contact metal layer.

2 more elements

An integrated circuit comprising:

a semiconductor structure comprising at least:
a substrate;
at least one semiconductor fin disposed on the substrate;
a disposable gate in contact with the at least one semiconductor fin;
a spacer disposed on the at least one semiconductor fin and in contact with the disposable gate;
source and drain regions epitaxially grown at least partially within the at least one semiconductor fin;
and
a first one of silicide and germanide disposed on and in contact with the source region;
and
a second one of one of silicide and germanide disposed on and in contact with the drain region.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/855,049Filed 27 Dec 2017

Priority

8 Sep 2016

Published

3 May 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification37 codes

H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 30/031
Of FETs having insulated gates [IGFET]: of thin-film transistors [TFT]
H10D 30/0318
Of thin-film transistors [TFT]: of vertical TFTs
H10D 30/6713
Having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device:…

Low resistance source-drain contacts using high temperature silicides

Life of this patent

Low resistance source-drain contacts using high temperature silicides

Life of this patent

Abstract

Claims20