Three terminal fuse structure created by oxygen vacancy traps in hafnium-based oxides
AssigneeInternational Business Machines Corporation
InventorsEduard A. Cartier, Chandrasekharan Kothandaraman
Life of this patent
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Abstract
A fuse structure includes a substrate, a gate dielectric formed on the substrate, a gate electrode formed on the gate dielectric, and first and second source/drain regions formed on the substrate on opposite sides with respect to the gate electrode, wherein the gate dielectric is configured such that a plurality of oxygen vacancies trapping respective charges are formed upon application of a pulse to the gate electrode.
Claims20
A fuse structure comprising:
- a substrate;
- a gate dielectric formed on the substrate;
- a gate electrode formed on the gate dielectric;
- and
- first and second source/drain regions formed on the substrate on opposite sides with respect to the gate electrode;
- wherein the first and second source/drain regions and gate electrode correspond to a transistor;
- and
- wherein the gate dielectric is configured such that a plurality of oxygen vacancies trapping respective charges are formed within the gate dielectric upon application of a pulse to the gate electrode;
- wherein the pulse is applied to the gate electrode while maintaining a source voltage and a drain voltage at constant levels;
- wherein a magnitude of the pulse applied to the gate electrode is negative relative to the source voltage;
- and
- wherein the application of the pulse to the gate electrode permanently changes a threshold voltage (Vt) of the transistor.
(canceled)
(canceled)
A one-time programmable memory device, comprising:
- a p-type field effect transistor (p-FET), the p-FET comprising:
- a gate dielectric formed on a substrate;
- a gate electrode formed on the gate dielectric;
- and
- first and second source/drain regions formed on the substrate on opposite sides with respect to the gate electrode;
- wherein the gate dielectric is configured such that a plurality of vacancies trapping respective charges are formed within the gate dielectric upon application of a pulse to the gate electrode;
- wherein the pulse is applied to the gate electrode while maintaining a source voltage and a drain voltage at constant levels;
- and
- wherein a magnitude of the pulse applied to the gate electrode is negative relative to the source voltage;
- and
- wherein the application of the pulse to the gate electrode permanently changes a threshold voltage (Vt) of the p-FET.
(canceled)
(canceled)
A method comprising:
- selecting a transistor to program, wherein the selected transistor comprises a gate dielectric formed on a substrate, and a gate electrode formed on the gate dielectric;
- and
- programming the selected transistor;
- wherein programming the selected transistor comprises:
- applying a pulse to the gate electrode of the selected transistor to form a plurality of vacancies in the gate dielectric trapping respective charges;
- wherein the pulse is applied to the gate electrode while maintaining a source voltage and a drain voltage at constant levels;
- and
- wherein a magnitude of the pulse applied to the gate electrode is negative relative to the source voltage;
- and
- wherein the programming permanently changes a threshold voltage (Vt) of the selected transistor.
(canceled)
(canceled)
Dependencies are inferred from the claim text.