Erase For Partially Programmed Blocks In Non-Volatile Memory
AssigneeSanDisk Technologies LLC
InventorsBiswajit Ray, Mohan Dunga, Changyuan Chen
Life of this patent
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Abstract
An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. At the end of successful erase verification, a subset of memory cells is read to detect an erase depth or level of the memory cells. If the erase depth check indicates that the subset memory cells are in a shallow erased condition, additional erasing and verification is performed.
Claims20
An apparatus, comprising:
- a control circuit having a memory interface for a non-volatile memory array, the control circuit configured to erase a plurality of non-volatile memory cells coupled to a plurality of word lines of the non-volatile memory array as part of an erase operation, the control circuit configured to perform a read operation to determine an erase depth of a subset of the non-volatile memory cells in response to successful verification of the plurality of non-volatile memory cells for an erased state, the control circuit configured to erase at least a portion of the plurality of non-volatile memory cells if the erase depth of the subset is above a threshold, the subset includes fewer than the plurality of non-volatile memory cells.
An apparatus, comprising:
- a plurality of word lines coupled to a plurality of non-volatile memory cells;
- and
- a control circuit having a memory interface for the plurality of non-volatile memory cells, the control circuit responds to the plurality of memory cells passing erase verification for an erase operation by reading from one or more of the word lines using a read reference voltage that is lower than an erase verify voltage, the erase circuit determines a number of bits of the one or more word lines having a threshold voltage above the read reference voltage and applies an erase voltage pulse to the plurality of non-volatile memory cells based on the number of bits exceeding a threshold.
A method, comprising:
- applying one or more erase voltage pulses to a plurality of non-volatile memory cells;
- after verifying that the plurality of non-volatile memory cells are erased based on a first reference voltage and prior to applying an additional erase voltage pulse, reading a subset of non-volatile memory cells for an erased condition based on a second reference voltage, the second reference voltage is lower than the first reference voltage, and the subset includes fewer than the plurality of non-volatile memory cells;
- and
- applying one or more additional erase voltage pulses to at least a portion of the plurality of non-volatile memory cells if the subset of non-volatile memory cells fails to verify for the erased condition based on the second reference voltage.
An apparatus, comprising:
- a plurality of word lines coupled to a plurality of non-volatile memory cells;
- means for determining an erase depth of a subset of non-volatile memory cells of the plurality after successfully verifying the plurality of non-volatile memory cells for an erased state, the subset of non-volatile memory cells includes fewer than the plurality of non-volatile memory cells;
- and
- means for erasing at least a portion of the plurality of non-volatile memory cells if the erase depth of the subset of non-volatile memory cells is above a threshold.
Dependencies are inferred from the claim text.