Memory device and clock training method thereof

A memory device comprising:

• a latch including an input buffer configured to receive a control signal from a host;
• and
• a sampler configured to sample the control signal provided from the input buffer in synchronization with a clock signal provided from the host;
• wherein in response to executing a training operation on the memory device that includes synchronization of the control signal at a reference time point of the clock signal, and wherein the clock signal does not transition after the reference time point, the training operation is executed based on a failure time point at which the sampler fails to sample the control signal at the reference time point.

A memory device comprising:

• a clock buffer configured to receive a clock signal from a host, wherein the clock signal does not transition after a reference time point;
• an input buffer configured to receive a control signal from the host;
• a sampler configured to sample the control signal provided from the input buffer in synchronization with the reference time point of the clock signal;
• and
• a command address latch that receives a command signal and an address signal from the host;
• a memory cell array in communication with the sampler and the command address latch, the memory cell array configured to store training data;
• wherein the control signal is synchronized with the clock signal in response to a control signal training operation initiated by the host;
• and
• wherein the command signal is synchronized with the clock signal in response to a command signal training operation initiated by the host.