Semiconductor device and error correction method
AssigneeMicron Technology, Inc.
InventorKazuhiko Kajigaya
Life of this patent
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Abstract
A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. The reference read write circuit is configured to generate a reference voltage in response to data stored in at least one of the plurality of memory cells. A plurality of sense amplifiers are each coupled to a respective memory cell of the plurality of memory cells. An error-correction code (ECC) control block may output an error signal when the ECC control block detects that it is unable to correct error data in one or more respective memory cells. The reference read write circuit may overwrite data in the at least one of the plurality of memory cells in response to the error signal.
Claims19
A method, comprising:
- judging a plurality of data values stored by selected first memory cells of a plurality of first memory cells and selected second memory cells of a plurality of second memory cells, by referring to a reference signal corresponding to reference data stored by at least one selected third memory cell of a plurality of third memory cells;
- detecting existence of an error exceeding error correction capability in the judged data values of at least one of the plurality of first memory cells or the plurality of second memory cells, wherein the judged data values of the plurality of first and second memory cells comprise an error correcting code;
- and
- writing the reference data to the at least one selected third memory cell in response to detecting the error exceeding error correction capability in the judged data values of at least one of the plurality of first memory cells or the plurality of second memory cells.
The method of claim 9, wherein generating the reference voltage includes supplying the reference voltage to a reference node, wherein the at least one of the plurality of memory cells includes a first and a second memory cell coupled to each other via the reference node.
The method of claim 9, further comprising storing data of a first logic value in a first memory cell and storing data of a second logic value in a second memory cell, wherein the at least one of the plurality of memory cells comprise the first and second memory cells.
The method of claim 9, wherein generating the reference voltage includes:
- coupling a first reference bit line to the first memory cell storing data of the first logic value;
- coupling a second reference bit line to the second memory cell storing data of the second logic value;
- and
- serially coupling first and second transistors between the first reference bit line and the second reference bit line, wherein the reference voltage is output from a connection node of the first transistor and the second transistor.
A method comprising:
- coupling a reference read/write circuit to a first memory cell to generate a reference voltage in response to data stored in the first memory cell;
- and
- detecting presence of an error in data stored in a second memory cell and outputting an error signal in response to being unable to correct the error in the data stored in the second memory cell, wherein the reference read/write circuit is configured to rewrite to the first memory cell in response to the error signal.
Dependencies are inferred from the claim text.