RRAM, and Methods of Storing and Retrieving Information for RRAM
AssigneeMicron Technology, Inc.
InventorAdam Johnson
Life of this patent
Estimating the term…
Abstract
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
Claims16
A method of storing and retrieving data for a resistive random access memory array, comprising:
- subdividing the resistive random access memory array into a plurality of memory bits, each memory bit comprising at least two memory cells;
- programming a memory bit by substantially simultaneously changing resistive states of all memory cells within the memory bit;
- and
- reading the memory bit by determining summed current through all memory cells within the memory bit.
A method of storing and retrieving data for a resistive random access memory array, comprising:
- subdividing the resistive random access memory array into a plurality of memory bits, each memory bit comprising a set of at least two coupled memory cells with all memory bits in the array having equivalent sets;
- programming a memory bit by substantially simultaneously changing resistive states of all the coupled memory cells within the set, each set of coupled memory cells comprised by a given individual memory bit being configured to be separately programmed relative to other sets of coupled memory cells comprised by others of the memory bits, the programming of each memory bit including addressing the set of coupled memory cells by paired wordlines and a single bitline or by paired bitlines and a single wordline;
- and
- reading the memory bit by determining summed current through all memory cells within the memory bit.
Dependencies are inferred from the claim text.